Senior ASIC Design Engineer (eInfochips Inc) at Arrow Electronics, Inc. summary:

The Senior ASIC Design Engineer at eInfochips is responsible for mapping multi-million gate SoC designs onto prototyping platforms, developing FPGA builds, and creating testbenches to simulate components. The role involves collaborating with cross-functional teams to validate SoC functionality and performance, with expertise required in FPGA design, RTL coding, and digital design concepts. Candidates should have a strong background in prototyping SoCs, networking protocols, and scripting, with a bachelor's or master's degree in electrical or computer engineering and extensive ASIC experience.

What candidate will Be Doing:

• Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.
• Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.
• Option to engage in block-level RTL design or block or top-level IP integration.
• Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC.

What we are looking for:

• A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.
• A comprehensive understanding of FPGA design , with proven expertise in partitioning multi-million gate designs across multiple FPGAs.
• Proficiency in synthesis, place, and route flows for FPGAs.
• An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC).
• Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs.
• A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development.

Preferred Qualifications

• Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms.
• A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols.
• Proficiency in prototyping ARM or RISCV CPUs.
• Exceptional scripting skills using languages such as TCL, Python, or Perl.

What's In It for You:

• At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package.
• Medical, Dental, Vision Insurance
• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off (including sick, holiday, vacation, etc.)
• Tuition Reimbursement
• Growth Opportunities
• And more!

Education:

• Bachelor's Degree

Work Arrangement Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location: Complete On-Site at San Jose, CA

About eInfochips:

eInfochips, an Arrow company (Fortune #133), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow's Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit for our portfolio of product engineering services across various industries & verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Keywords:

ASIC design, FPGA prototyping, SoC integration, RTL coding, Verilog, SystemVerilog, digital design, networking protocols, synthesis place and route, TCL scripting, Python scripting